Research Article  Open Access
Indranil Hatai, Indrajit Chakrabarti, "A New HighPerformance Digital FM Modulator and Demodulator for SoftwareDefined Radio and Its FPGA Implementation", International Journal of Reconfigurable Computing, vol. 2011, Article ID 342532, 10 pages, 2011. https://doi.org/10.1155/2011/342532
A New HighPerformance Digital FM Modulator and Demodulator for SoftwareDefined Radio and Its FPGA Implementation
Abstract
This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a highspeed, area optimized and lowpower features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarterwave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP307ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.
1. Introduction
In the prevalent audio broadcasting applications like private mobile radio (PMR) and digital audio broadcastingterrestrial (DABT) standards, excellent clarity along with the source stability is required for the voice transmission. Frequency modulation (FM) scheme is used in most of these standards. Traditionally, FM signal generation was performed using some analog components to support the audio broadcasting standards. But difficulties arose in analog FM modulation scheme due to the use of the voltagecontrolled oscillator (VCO). Using the VCO, it is very difficult to obtain a good clarity as well as source stability in FMmodulated or demodulated signal as VCO suffers from lack of linearity over the desired frequency range. Therefore, digital implementation of FM modulation scheme has evolved to replace the traditional analog counterpart. Nowadays, to get superior performance and good voice clarity in any audio broadcasting system, digital FM modulation and demodulation technique is widely used. To ensure linearity over the entire frequency range, designers choose to replace the VCO by a DDFS, sometimes referred to as a numerically controlled oscillator (NCO). Considerable research has been performed on different digital FM modulator architecture. Some of these have laid stress on reducing the distortion effects of quantization noise, which occurs due to the bit resolution at the input and output of the DDFS [1]. Some of them have discussed the area optimization and lowpower consumption [2–4] as main objective. In the present work, one highspeed, lowpower, and reducedarea digital FM modulator has been implemented in the FPGA device to support the audio broadcasting system in softwaredefined radio (SDR) system.
There exist various architectures [5–14] for implementing digital FM demodulator into a single chip, although their performance has mostly been limited by analog signal processing accuracy. The basic fundamentals behind FM demodulation are how to discriminate accurately a small frequency deviation of the FMmodulated signal from its center frequency. PLL method is one of the popular techniques for FM demodulation. It can be easily implemented in integrated forms, but sudden departure from its linearity property of the VCO in some portions of the frequency range degrades the overall system performance. Digital PLLs provide a better possible solution to overcome some of the bottlenecks of analog PLLs [15]. Due to this, in the present FM demodulators, the digital phaselocked loop (DPLL) is mostly used for accomplishing the frequency discrimination. The DPLL tracks the variations in the received signal phase and frequency. There are also some other techniques by which the frequency can be computed from the ratio of the inphase (I) and the quadrature (Q) components. Modern communication revolves around highspeed, high data rate transmission and reception. DPLLbased implementation of FM demodulators in DSP often does not meet such demanding requirements of a wireless communication system. An alternative solution is to implement it in FPGA due to its flexibility and modularity. A reducedarea, lowpower, and highspeed linear digital FM demodulator using the DPLL technique [5, 6] has been implemented towards the development of an SDR system. Componentwise improvements have been carried out in this work to get compact architecture, a faster system clock, and achieve a less power consumption while compared with existing implementations of digital FM demodulator. In SDR application lessarea and lowpower consumption with high data rate support is the key concern. Targeting to the next generation SDRbased wireless communication transceiver, in this work all the basic components of DPLLbased FM demodulator are fully optimized without losing the system output behavior in comparison with the previous DPLLbased FM demodulator implementations.
The present paper is as follows. Section 2 describes the principle and architecture of FM modulator and DPLLbased FM demodulator along with the architecture of individual component of FM modulator and DPLLbased FM demodulator, and in Section 3, FPGA implementation results in terms of synthesis results, simulation results, onchipverified results, and comparison results are mentioned. Conclusions are summarized in Section 4.
2. Architecture of Digital FM Modulator and DPLLBased FM Demodulator
2.1. FM Modulator
In the FM modulation technique, which is a kind of angle modulation methods, the instantaneous frequency of the carrier signal varies linearly with the basebandmodulated message signal as follows: where is the amplitude of the carrier, is the carrier frequency, and is the frequency deviation constant. The architecture of the FM modulator is as shown in Figure 1.
The FM modulator consists of (1) an FM data generator, (2) an interpolator with interpolation factor of 32, (3) an accumulator, and (4) a DDFS block. The FCW signal has been used for generating different carrier frequency. The accumulator block adds the instantaneous frequency of the input audio signal with the selected carrier frequency. And finally DDFS block takes this frequency as an input and generates the FMmodulated signal. The architecture of the DDFS block has been discussed in the later section.
(1) FM Data Generator
Usually, FM modulation scheme is used to support audio processing in the audio broadcasting system. Generally, the audio signal is processed in the range between 44 Kbps and 320 Kbps. The FM input data is sampled at each FM symbol clock and stored in a register for further processing. The digitized input data is passed through a serialtoparallel converter to generate the 8bit FM input data. The architecture for FM data generator is shown in Figure 2.
(2) Interpolator
Interpolator block is used in FM modulator to get a better power level for the FM transmission. In this work, an interpolation factor of 32 has been used between two consecutive audio samples. The circuits first calculate the difference and then divide the remainder by 32. To perform the division by 32, the new FM input data is shifted by one bit before and by four bits after the subtraction. Then the output is added with the previous input data on every symbol clock. One subtractor, one adder, and some registers are required to perform the interpolation operation in hardware. The architecture for the interpolator is as shown in Figure 3.
The power spectral density of the designed FM modulator has been shown in Figure 4.
2.2. DPLLBased FM Demodulator
Operation of the digital phaselocked loop as an important component of FM demodulator has been conceived in the early 1970s [16, 17]. The input frequency modulated signal can be expressed as follows: Feedback loop mechanism of the PLL makes the DDFS to generate a sinusoidal signal with the same frequency as that of , where The output of the phase detector, which is the product of these two signals, is found using familiar trigonometric identity: where is the gain of the phase detector. The first term in (4) corresponds to the highfrequency component. The second term corresponds to the phase difference between and . The phase difference, that is, between the modulated signal and the carrier produces the desired original signal with frequency .
The single most important point to realize while designing the PLL is that it is a feedback system and, hence, it is characterized mathematically by the same equations that are applied to other more conventional feedback control systems. The mathematical model of the digital PLL system can be derived to analyze the transient and steady state responses. The block diagram of a typical digital PLL system in domain [18] (discrete domain) and its transformation in domain [19] (continuous time) is shown in Figure 5.
The transfer function of the system is The secondorder DPLL system improves the performance of the loop in terms of speed and locking range as compared to the firstorder DPLL system. That is why the DPLL system used here is a secondorder system. The unit step response curve is obtained using MATLAB for the system shown in Figure 6. From the figure it can be seen that the system is stable with overshoots at the transient state.
The complete FM receiver consists of the basic building blocks as shown in Figure 7. The FM receiver consists of four basic parts: (1) Phase Detector (PD), (2) Loop Filter (LF), (3) Direct Digital Frequency Synthesizer (DDFS), and (4) FIR Filter.
3. Phase Detector
The phase detector is used to detect the phase error between the incoming frequencymodulated signal from the ADC and the output frequency generated from the DDFS. This operation needs one register and one multiplier module. The modified Radix4 BoothEncoded Wallacetree multiplier [20–22] architecture is used instead of a signed arithmetic multiplier. This architecture has been chosen because it reduces the number of partial products to for an bit multiplication process. Conventionally, in a radix4 Booth multiplier, there are three basic steps to be followed: (1) generate the reduced partial product according to Booth’s algorithm, (2) reduce the number of additions of the partial product, and finally (3) use a highspeed adder like carry lookahead adder (CLA) for the last two rows of the partial product tree. For the signed multiplication operation, the sign extension scheme has been combined with Booth’s algorithm which is known as the modified Booth algorithm. To multiply by using radix4modified Booth’s algorithm, the three bits of the multiplier part will be grouped and will be encoded into one of as per Table 1.

The modified Booth encoder, which is shown in Figure 8(a), is implemented using some logic gates. The partial products are generated using the Booth decoder as shown in Figure 8(b). The block diagram of the Boothencoded Wallace tree multiplier [21] is shown in Figure 9.
While generating the partial products from the modified booth decoder, then we followed FadaviArdekani’s [23] sign extension prevention. Wallace Tree Carry Save Adder structure [24] has been used for adding the with in a parallel fashion until the last two rows remained. The last two rows have been added using a very highspeed Carry Lookahead Adder (CLA) to obtain the final multiplication result. The architecture as a block diagram of the designed 8 × 8 bit multiplier using modified Booth’s algorithm is shown in Figure 9. Here the multiplicand is and multiplier is input is encoded by Booth encoder to generate the encoded signal which is used by the Booths decoder to generate the partial product term by taking as the input. After generating all the partial products, the Wallace tree performs the addition operation in a parallel fashion. Finally CLA is used to complete the multiplication procedure of the two 8bit numbers.
4. Loop Filter
Loop filter, which is a firstorder lowpass filter, is used to remove the highfrequency components of the output of the phase detector given by (4). Figure 10 shows the block diagram of the firstorder loop filter used in the DPLLbased FM demodulator system. The transfer function of the loop filter is given by
Equation (6) can be implemented in hardware by the addition of the output signal from the phase detector (PD_OUT) and the register output multiplied by a coefficient , which is chosen to ensure the system stability. Multiplication by a factor of 1/16 has been implemented by 4bit right shift instead of a multiplier.
5. Direct Digital Frequency Synthesizer
DDFS finds wide use as a component in modern communication system, radio detector, electronic warfare, high precision measurement system, and high precision biomedical applications. DDFS accepts arbitrary frequency as its reference frequency depending on the frequency control word and generates one or more frequencies. The DDFS architecture was first given in [25]. The arithmetic operations required to build a DDFS are a phase accumulator which generates the phase for generating the cosine waveform and a phase to amplitude converter. Various researches have been performed to design a highperformance circuit for phasetoamplitude conversion as summarized in [26–28]. The quarterwave symmetry ROM technique is very useful where a very low phase resolution has been used [29]. Many ROM compression techniques have been proposed, but for lowresolution bit, these techniques are not suitable as they maximize the error. This DDFS has been designed for waveform synthesis in DPLLbased FM demodulator. The ROMbased DDFS has been designed for use in the DPLLbased FM demodulator. In DPLLbased FM demodulator, the quadrature output from the DDFS is not required. Due to this fact, the ROMbased architecture (LUT) is considered to be superior to the CORDICbased architecture [30] for the phasetoamplitude conversion. To overcome the disadvantages of ROMbased DDFS, namely, highpower consumption and low speed, a pipelined ROMbased DDFS approach has been considered in the present work. Pipeline technique will help reduce the power consumption and also maximize the operating frequency. In the present work, the designed pipelined lookup tablebased DDFS architecture is used as shown in Figure 11.
The DDFS consists of a phase accumulator, a ROM lookup table, two 1’s complementers, a pipelined register, and an XOR gate. The designed DDFS has a free running frequency of 1 MHz and requires 1024 sample values to define one cycle of a cosine signal. The DDFS generates the cosine signal waveform by addressing the cosine ROM LUT at a frequency set by an 18bit control word. If the reference system clock (Fclk) is set to 100 MHz, then the frequency resolution will be 381.468 Hz. According to the accumulation rate in phase accumulator set by the FCW, the ROM produces the cosine waveform at that programmed frequency. In this implementation, the frequency control word (FCW) and the output bits have been chosen to be 18 bits and 8 bits, which provides spurious free dynamic range (SFDR) of 64.3 dB. As the design is pipelined, the frequency switching will suffer from 2clock cycle latency.
MATLAB 7.4.0 version is used for the performance analysis of the designed two DDFS blocks. The floating point cosine wave generated using the MATLAB inbuilt function and cosine wave generated by proposed pipelined ROMbased DDFS has been analyzed. The results are shown in Figure 12. Hence the FLTPNT_COSINE is the MATLABgenerated cosine wave and FXDPOINT_COSINE is the cosine wave generated by our proposed ROMbased DDFS. The error between these two signals in the first quadrant has been shown in Figure 13 (as quarter wave symmetry property has been adopted). The minimum error is −0.0088 and maximum error is 0.0089 which is nothing but the quantization error (as 8 bits of amplitude has been considered in proposed design).
6. Fir Filter
At the last stage of the receiver, a lowpass Finite Impulse Response (FIR) filter is used to perform the signal shaping. Here a 16tap transposed FIR filter architecture [31] is used, as shown in Figure 14. This filter is essentially an averaging filter since its output is equal to the average value of its input values over the last tap samples where n is the number of taps used. As in direct form digital FIR filter the total propagation delay of the circuit increases more due to the addition of the 16 data samples, a transposed FIR filter architecture is chosen [32–34] in the present implementation. Here the coefficients are the same 1/16, and in reality 1/16 can be implemented by just 4bit right shift operation. Hence no multiplier is required.
7. FPGA Implementation Details
7.1. Synthesis Results
The proposed FM demodulator has been described using the Verilog hardware description language and Xilinx ISE 9.2i is used for synthesis and FPGA implementation. Xilinx XCV2vp307FF896 device has been used as the target device for FPGA implementation, XST has been used as a synthesis tool, and XPower has been used for power calculation. The power is being calculated by simulationbased switching activities of all the signals. The synthesis results for the FM modulator and demodulator have been listed in Table 2. Table 3 listed the detailed dynamic power analysis result by applying a 100 Mbps data rate to the FM modulator and demodulator. Table 4 shows the componentwise implementation reports.



7.2. Simulation Results
For the post place and route simulation in FPGA, the ModelsimXe 6.3c Starter version from Mentor Graphics is used as a logic simulator. The modulated response of a 10 KHz triangular wave is shown in Figure 15. The demodulated response of the FMmodulated signal is as shown in Figure 16. Carrier frequency has been taken to be 1.5 MHz by setting the frequency control word to 512 and the input clock to 100 MHz with a modulation index of 10. In Figure 13, the signals from the top represent the input triangular wave (TRIANG_INPUT), the frequency control word (FCW) for setting the carrier frequency, and the modulated input data (FM_MOD). For the triangular wave the modulated signals from the top are the demodulated output data (FM_DEMOD), the modulated input data (FM_MOD), the FIR filter output (TRI_FIR), the loop filter output data (TRI_LOOP), the DDS output data (TRI_DDS), and finally for phase detector output (TRI_PD) shown in Figure 16. At the initial simulation phase, the demodulated output overshoots since the phase synchronization is in convergence phase and after that the system is stable.
7.3. OnChipVerified Results
The designed system has been implemented using the Xilinx impact tool to the Virtex2 Pro University Board. Xilinx ChipscopePro 9.2i has been used for capturing the demodulating (FM_DEMOD) data for verifying the FPGA implementation result of the designed circuit. Here 2048 samples of the output have been captured after implementing the design into FPGA. The captured output results are shown in Figure 17 for triangular input. It can be concluded from inspection of these figures that the designed circuit can effectively demodulate the FM input signal back to its original form.
7.4. Comparison Results
By optimizing the basic components of the FM demodulator, the reduction of the hardware usage and improvement in the performance has been done. Table 5 has summarized the comparison result with other ROM compression techniques while implementing a direct digital synthesis. In this context, Table 6 shows the comparison result with other existing FPGA implementations of FM demodulator [7, 11].
 
*where is the accumulator length, is the word length of truncated phase, and is the word length of DDFS output. 

The proposed circuit has been synthesized using the Leonardo Spectrum 2005b.24 Level 3 from Mentor Graphics using the TSMC 350 nm (typical) as a target technology library. During the synthesis, speed has been considered as the main constraint for the designed circuit. Another FM receiver circuit has also been designed and synthesized using the Leonardo Spectrum 2004a.63 from Mentor Graphics and TSMC 350 nm (Fast) as a target technology library. From Tables 7 and 8, it is observed that the FM demodulator designed in this chapter is better in performance compared to the available DPLLbased FM demodulator [5, 6].


8. Conclusions
A new highperformance digital FM modulator and a digital phaselocked loopbased FM demodulator have been proposed in this paper. The FM modulator and demodulator are designed to satisfy the constraint for the application in personal wireless communication and digital audio broadcasting. Individual componentwise optimization has made the overall design superior than other implementations. FPGA implementation of the proposed design has been carried out for quick prototyping of the digital FM modulator and demodulator chip. The simulation and synthesis result of FM modulator shows that the digital up conversion is very much possible as it can achieve maximum clock frequency of 334.5 MHz. From the onchipverified result it can be clearly seen that the proposed FM demodulator can demodulate the signal back in its original form by consuming only 6.4 K equivalent gate count. The comparison results for both FPGA and ASIC implementations have shown that the proposed design is superior to the existing digital FM chips. Hence it is concluded that the designed highperformance FM modulator and demodulator can be easily fitted into the next generation softwaredefined radiobased handset where low power and minimum hardware utilization with the maximum clock frequency are desired features.
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Copyright
Copyright © 2011 Indranil Hatai and Indrajit Chakrabarti. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.